module top
(
    input          input_clk,     
    input          sys_rst_n, 

    input          miso,
    output         cs,
    output         sck,
    output         mosi,

    input          cs_in,
    input          clk_in,
    input          mosi_in,
    output         miso_out,
    output         [7:0] out
);

// assign cs = cs_in;
// assign sck = clk_in;
// assign mosi = mosi_in;
// assign miso_out = miso;

assign out[0] = cs;
assign out[1] = miso;
assign out[2] = mosi;
assign out[3] = sck;

wire  sys_clk;   
wire  uart_clk;  
wire  clk_5m;    
wire  clk_20m;   
wire  extlock;   

//		Clock name	| Frequency 	| Phase shift
//		C0        	| 100.000000MHZ	| 0  DEG     
//		C1        	| 200.000000MHZ	| 0  DEG     
//		C2        	| 5.000000  MHZ	| 0  DEG     
//		C3        	| 20.000000 MHZ	| 0  DEG 
PLL u_pll(
    .refclk   (input_clk ),
    .reset    (~sys_rst_n),
    .extlock  (extlock 	 ),
    .clk0_out (O_clk0    ),
    .clk1_out (O_clk1    ),
    .clk2_out (O_clk2    ),
    .clk3_out (O_clk3    )
); 
assign sys_clk     = O_clk0; 
assign uart_clk    = O_clk1; 
assign clk_5m      = O_clk2;
assign clk_20m     = O_clk3;


spi_send_n 
spi_send_n_inst
(
    .sys_clk    (sys_clk    ),
    .low_clk    (clk_20m    ),
    .sys_rst_n  (extlock    ),
    .miso       (miso       ),
    .cs1        (cs         ),
    .sck        (sck        ),
    .mosi       (mosi       ),
    .spi_rst    (spi_rst    )
);



endmodule

